This invention relates to semiconductor devices and their fabrication; and more particularly, to an integrated injection logic circuit cell structure and a method for fabricating it with a greater ease resulting partially from a reduction in the number of masking steps.
There is considerable interest currently in semiconductor digital integrated circuits. Such circuits can perform a variety of logic functions which are fundamental to many significant applications such as computers. Known logic circuits include transistor-transistor logic, resistor-transistor logic and diode-transistor logic. Such logic circuits are characterized by a power supply dissipating resistor connected between a power supply and a switching element of the logic circuit. It is often desired to incorporate logic circuits into a large scale integrated circuit structure. In large scale integration, components such as resistors are undesirable because of the relatively large amount of space they usually require.
It is known that such power supply dissipating resistors can be replaced by a transistor. One form of such a circuit is called an injection logic circuit and includes a two-complementary transistor cell which performs a logical inversion. In its usual form, an NPN switching transistor in the cell has its base connected to an input terminal, its collector connected to an output terminal and its emitter connected to ground. A complementary PNP injector transistor is the other transistor in the cell and has its base connected to ground, its emitter connected to a positive voltage source and its collector connected to the base of the switching transistor. In integrated logic circuits, cells are usually connected sequentially by connecting the collector of the switching transistor to the base of a subsequent switching transistor.
In operation, the emitter-base junction of the injector transistor is forward-biased because the base is grounded and the emitter is connected to the positive voltage source. The logical input voltage applied to the base of the switching transistor determines whether the emitter-base junction of the switching transistor is biased on or off. When a logical "1" forward-biases the junction, the current from the collector of the injector transistor flows through the emitter-base path of the switching transistor. The switching transistor conducts in saturation with current supplied by the PNP injector transistor of the next stage and the collector is at a potential equal to the collector-to-emitter saturation voltage of the switching transistor, or a logical "0. " Thus a logical "1" has been inverted to a logical "0. " when a logical "0" input is applied to the emitter-base junction of the switching transistor, that transistor is turned off and the current from the injector transistor flows out the input through a previous injection logic cell to ground. The collector of the switching transistor provides a logical " 1" output because the collector is connected to the voltage source through a subsequent forward-biased injector transistor of a subsequent cell.
It is further known to fabricate p-n junction isolated integrated injection logic circuit structures using two masking steps to form the impurity zones of the transistor. Such methods are described in an article by Horst H. Berger and Siegfried K. Wiedmann entitled "Merged Transistor Logic (MTL) -- A low cost Bipolar Logic Concept" and in an article by Kees Hart and Arie Slob entitled "Integrated Injection Logic: A New Approach to LSI." Both articles appear in the IEEE Journal of Solid State Circuits, October 1972 at pages 340 and 346, respectively.
Integrated injection logic circuit structures are characterized by having impurity zones which serve as functional parts of two different transistors. That is, the same impurity zone serves as the base of the injection transistor and the emitter of the switching transistor. Also, another zone serves as both the collector of the injection transistor and the base of the switching transistor. Further, when multiple outputs are desired, integrated injection logic circuit structures have a switching transistor with multiple collectors. The multiple collector zones are formed into the surface of the structure and the emitter is buried. This is an inverted transistor structure when compared to a standard buried collector structure.
It would be desirable to improve upon integrated injection logic circuit cell parameters such as size, speed and packing density. Additionally, it would be desirable to reduce the number of masking steps to fabricate injection logic circuits with two levels of metallization. Two levels of metallization are often advantageous in large scale integration of such circuits. Elimination of a masking step usually increases yield and permits smaller size by eliminating re-registration tolerances.
The prior art includes U.S. Pat. No. 3,648,125 issued to D. L. Peltzer on Mar. 7, 1972 which teaches a method of fabricating integrated circuits with oxide isolation. Transistors, diodes and resistors formed in accordance with this patent have smaller size, higher speed and higher packing density than those devices formed using p-n junction isolation.
Straightforward application of the oxide isolation technique to the fabrication of injection logic circuits suggests laterally surrounding each injection logic circuit cell with an oxide region. This reduces the capacitance associated with the p-n junction isolation laterally surrounding the cell. However, such use of oxide isolation does not yield the desired reduction in size.